From GitHub
- GitHub stars
- 5
- Last code update
- 2026-08-05
Interactive virtual boards to help teach and learn Verilog.
Why it made the shelf
It is a developer tool for simulating hardware boards and learning Verilog.
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Official signals
Sourced facts from the places where this tool ships.
From GitHub
Behind the tool
People, backing, growth, and ownership. Every claim links to its source.
Source review queued
Public trail
1 reference from 1 publisher.